1. Field of the Invention
The present invention relates generally to an integrated memory device and particularly to memory circuits comprising multiple types of memory. More particularly, the present invention relates to an integrated circuit memory device comprising random access memory and read only memory in a single package.
2. Background of the Invention
Most electronic systems such as computers, calculators, watches, physiological monitors and most types of consumer electronics have circuit boards in which electronic components are mounted. The size of the circuit board generally dictates how many components can be mounted on it. Often, the number of features that can be incorporated into an electronic device depends on the number of electronic components that can fit on the circuit board. Thus, a major design consideration in many electronic systems is the circuit board area, or "real estate," available for holding electronic components. For example, increasing the amount of memory in a computer can enable the computer to run larger, more complex application programs but often requires adding extra memory chips, which occupy circuit board space. In some electronic systems, the circuit board size may be increased to add functionality. In other systems where space is a premium, however, the circuit board area cannot be increased. For example, portable and handheld computers, calculators, handheld video games, and computer expansion cards such as Personal Computer Memory Card International Association (PCMCIA) cards (or "PC-cards"), have a limited amount of space that can be allocated to circuit boards and other system components.
A common electronic component known as an integrated circuit (IC) is manufactured by etching interconnected transistors onto a semiconductor die. Conductive metallic leads are then connected to selected portions of the circuit, and the semiconductor is encased in a shell made of metal, plastic, ceramic, or other material. The resulting IC "package" can be mounted onto a printed circuit board and connected to other IC's and electronic devices via the package leads. Transistors can be etched microscopically small and packed closely together, resulting in a relatively small semiconductor die. Because IC's must be mounted (or "stuffed") onto printed circuit boards either by hand or by machine, however, the package size and leads must be large enough to be easily handled. Consequently, typical IC packages are much larger than the actual semiconductor die, leaving empty space within the IC package.
Many microprocessor or microcontroller-based electronic devices require a standard set of "glue logic" IC's to augment and support the functions of the microprocessor. Examples of such glue logic IC's include memory devices like read only memory (ROM), random access memory (RAM), input/output chips, and analog/digital converters. For such a system to fit onto a small circuit board, such as that of a PC-card, a significant amount of real estate is required simply for the glue logic, leaving precious little space for additional circuitry.
U.S. Pat. No. 4,095,281 attempts to alleviate the tradeoff between limited circuit board space and the number of IC's desired to mounted on the board by disclosing a memory cell for storing a single binary digit (or "bit") of data that may operate in both ROM and RAM modes. A single memory device may incorporate an array of these combination memory cells, so that RAM and ROM functions are included within a single IC package. Previous memory devices generally included only one type of memory technology, requiring circuit boards to include separate IC packages for RAM and ROM. The combination memory cells can thus reduce the circuit board area that must be allocated for memory.
A potential disadvantage to the patent is that each memory cell requires a larger number of transistors than most conventional RAM and ROM cells. A typical ROM cell requires a single transistor, while a typical RAM cell may require up to four transistors. The patented combination memory cell requires anywhere from six to eight transistors per cell, however, possibly increasing the cost of manufacturing the device significantly. In addition, a large number of the transistors may be essentially wasted if some memory cells are used only for RAM or only for ROM.
U.S. Pat. Nos. 4,004,286, 4,575,819, 4,855,803, and 4,995,004 generally disclose memory cells capable of operating as either RAM or ROM. The particular ROM cells disclosed by these patents are permanent ROM's. Designers often prefer programmable ROM devices over permanent ROM devices, however, because programmable ROM's allow the designers to change the ROM contents when developing electronic systems that use ROM. Programmable ROM's also permit efficiently upgrading existing systems in the field.
U.S. Pat. Nos. 3,753,242 and 4,610,000 generally disclose devices that contain RAM and ROM portions. In U.S. Pat. No. 3,753,242, the RAM is divided into a plurality of memory segments, each of which is the same size as the ROM. The ROM is then used as a replacement for one of the RAM segments, so that the ROM handles memory requests directed to the replaced RAM segment. Because the replaced RAM segment cannot be accessed during a memory transaction, the RAM and ROM share the same address space, meaning that any particular memory address may correspond to either the RAM or the ROM, but not both. Because the ROM must have the same storage capacity as only one segment of the RAM, the size of the ROM is thereby limited to a fraction of the size of the RAM. As a result, the device requires extensive and costly decoding circuitry to determine whether an address is directed to RAM or ROM.
U.S. Pat. No. 4,610,000 teaches a read only memory that incorporates a special "patch" ROM and a special "patch" RAM. The patch memories are used to update the main ROM data, which is permanently encoded. To update a particular location in the main ROM, data are written to a corresponding location in the patch memory, which is thereafter accessed in lieu of the updated main ROM location. The system requires that the patch memories share an address space with the main ROM, however, requiring extensive control circuitry to determine which memory device to access for each memory transaction.
Accordingly, there is a need for a space-efficient memory device that incorporates multiple types of memory technologies in a single IC package. Preferably, the IC package and transistor technologies used for the device should conform to common industry standards, in order to minimize the cost of volume production. Further, the device should possess a standard signal interface to ensure compatibility with a wide array of memory systems and should not require extensive decoding and control circuitry. Despite the apparent advantages that such a memory device would provide, to date, no such device has been developed that provides these features.